There is a large segment of the data processing prior art directed to the transmission of data in fields or blocks, via parallel channels and busses, between processors, storage units, buffers, display terminals, input/output devices and the like. Some examples of typical prior art references in this environment include U.S. Pat. No. 4,126,897 entitled "Request Forwarding System" issued Nov. 21, 1978, to Capowski et al which describes a system wherein requests are forwarded from plural input/output channels to shared main storage. Variation in word widths are identified by tags such that "EOT" represents a "1-wide" request and a "QW" tag represents a "4-wide" request.
In U.S. Pat. No. 4,057,846 entitled "Bus Steering Structure for Low Cost Pipelined Processor Systems", issued Nov. 8, 1977, to Cockerill et al, a system is described including logic circuitry which provides a control function to steer data over the proper bus structures for interconnecting the processor, the memory and the input/output devices. No variable word problems are involved.
Likewise, Misunas et al in U.S. Pat. No. 4,174,536 discloses a system with a message routing switch wherein serial and parallel interfaces are associated with input/output ports. Davis et al in U.S. Pat. No. 4,075,691 and Larson et al in U.S. Pat. No. 4,079,452 show control systems using serial interface adapters and parallel interface adapters. Labeye-Voisin et al in U.S. Pat. No. 4,115,856 and Hostein in U.S. Pat. No. 4,034,346 show interfaces using parallel to serial conversion.
U.S. Pat. No. 4,159,534 to Gelson, Jr. et al, U.S. Pat. No. 4,070,710 to Sukonick et al, U.S. Pat. No. 4,004,283 to Bennett et al, U.S. Pat. No. 4,133,030 to Huettner et al, U.S. Pat. No. 4,205,373 to Shah et al, and U.S. Pat. No. 4,128,883 to Duke et al show systems using device, channel and interface adapters for coupling to a bus. In U.S. Pat. No. 3,949,375 to Ciarlo, a pair of 16-bit registers couple on an input/output bus to various display devices. In U.S. Pat. No. 3,500,466 to Carleton, a multiplexer is shown which couples different data sets through bit buffers to a common multi-line bus, and in U.S. Pat. No. 3,665,409 to Miller et al, a signal translator is shown for "skewing" or shifting data.
A particular application wherein it would be advantageous to interface between a variable width data bus and a variable width data field is in a bit-buffered display system of the type which provides high speed, high function text and graphics. The above-referenced application Ser. No. 06/394,044 filed by Dill et al discloses a general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N.sub.C and a data field of N.sub.f, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N.sub.f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at postition 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus.
The structure disclosed in the Dill et al application includes a modulo N.sub.C combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a substraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit N.sub.C. A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.
The subject invention is an improvement which extends the basic concepts disclosed in the above-referenced application Ser. No. 06/394,044 by Dill et al. That architecture of "scan line on all chips" which employs only one bit per chip has a number of attractive features, particularly in the simplicity of the chips and the macro nature of the additional required functions. However, it is quite restrictive in the allowable screen formats and tradeoff with data path width. In addition, in this one bit per chip organization, no special features were provided to control wrapping at the right hand edge of the scan lines, i.e. between logical segment boundaries. This would have to be done separately, otherwise inconsistent and sometimes very undesirable wrapping effects would be obtained. For instance, for all segment boundaries which do not occur at the highest column address, any 16 bit data word which crosses such a segment boundary will automatically wrap to the next scan line if the bit column address is incremented in the usual fashion. This is highly undesirable. Furthermore, for the segment boundary occurring at the maximum value of column address, a 16 bit word which maps across this boundary will wrap to a scan line three scan line positions above the intended line. This can be visualized by referring to FIG. 1 which shows the mapping of sixteen 64K.times.1 memory chips to the CRT screen. As can be seen in that figure, a column contains bits for four scan lines and incrementing the column address from maximum to zero selects the last then the first scan line, respectively, of that column. All of these effects are undesirable and are eliminated in the invention to be described. Furthermore, the restrictions on format versus data path width can be greatly reduced by adding a small amount of additional function to the chips. Of course, by adding more functions, all restrictions can be eventually eliminated, but the chip would be overly complex. The approach taken by this invention is to organize and operate the memory chips with either 32, 64, 128 or 256 bit wide segments (for the example of 64K chips), also externally selectable.